(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of reducing the risk of punch through current for a metal oxide semiconductor field effect transistor (MOSFET), device, via formation of a pocket region formed after composite spacer formation.
(2) Description of Prior Art
The emergence of MOSFET devices featuring sub−0.18 um channel lengths, has led to source/drain engineering procedures such procedures used to form pocket, or halo regions. The narrowing space between a source/drain region, experienced with short channel lengths, can result in unwanted punch through current generated by the close proximity of the source/drain depletion regions. A method used to reduce the risk of punch through has been the formation of pocket, or halo regions, surrounding the source/drain regions. These regions comprised with the same conductivity type as the semiconductor substrate or well region, but featuring a higher dopant level than the semiconductor substrate or well region, reduce the extent of depletion region when compared to depletion regions formed at the junctions of the non -pocket structures, thus resulting in less punch through current. However the increased dopant concentration of the pocket region adversely influences MOSFET performance via the increased junction capacitance. Therefore trade-offs between yield, less punch through current, and performance, increased junction capacitance, arise when implementing pocket or halo regions for short channel MOSFET devices.
This invention will describe a novel process sequence for implementation of a punch through region for a short channel MOSFET device. This invention will feature the formation of a pocket or punch through region at a specific point of the MOSFET fabrication sequence, after composite insulator spacer and heavily doped source/drain formation. This process sequence, also featuring selective removal of a composite insulator spacer component, offers reduced risk of punch through current, with less impact on junction capacitance. Prior art such as Gupta et al, in U.S. Pat. No. 6,391,732 B1, Pradeep et al, in U.S. Pat. No. 6,346,468 B1, Rodder et al, in U.S. Pat. No. 6,306,712 B1, Eiten, in U.S. Pat. No. 6,030,871, and Richards, Jr, et al, in U.S. Pat. No. 5,786,620, describe methods of forming composite insulator spacers, as well as methods of forming implanted pocket regions. However none of the prior art describe the novel process sequence employed in the present invention in which a pocket implant region is formed in a specific region of the MOSFET device, after composite insulator and heavily doped source/drain formation, allowing reduced punch though leakage to be obtained with less impact on performance degrading junction capacitance.